This invention relates to programmable logic integrated circuit devices (xe2x80x9cPLDsxe2x80x9d), and more particularly to memory circuitry for use on PLDs which a user of the PLD can use for various purposes during normal logic operation of the PLD.
Programmable logic devices having relatively large blocks of memory in addition to the usual programmable logic and programmable interconnect are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,550,782, Cliff et al. U.S. Pat. No. 5,689,195, Heile U.S. Pat. No. 6,020,759, Heile U.S. Pat. No. 6,144,573, and Heile U.S. patent application Ser. No. 09/389,995, filed Sep. 2, 1999. The above-mentioned blocks of memory can be connected to the programmable logic and/or input/output (xe2x80x9cI/Oxe2x80x9d) pins of the device via the programmable interconnect. Such blocks of memory can be used for read-only memory (xe2x80x9cROMxe2x80x9d), random access memory (xe2x80x9cRAMxe2x80x9d), content-addressable memory (xe2x80x9cCAMxe2x80x9d), product-term (p-term) logic, etc. It is known that such blocks of memory can have programmably variable width and depth. For example, a 2 K-bit memory can be configured as 2K one-bit words (xe2x80x9c2Kxc3x971xe2x80x9d), 1K two-bit words (xe2x80x9c1Kxc3x972xe2x80x9d), 512 four-bit words (xe2x80x9c512xc3x974xe2x80x9d), 256 eight-bit words (xe2x80x9c56xc3x978xe2x80x9d), 128 16-bit words (xe2x80x9c128xc3x9716xe2x80x9d), etc. It is also known that such blocks of memory can be provided with separate read and write ports so that reading and writing can be done independently at the same time (so-called dual-port operation).
The known programmable logic device memory arrangements of the type described above are sometimes difficult to fully utilize. For example, if a first-in/first-out (xe2x80x9cFIFOxe2x80x9d) memory having a capacity of eight words of eight bits each (i.e., an 8xc3x978 FIFO) is needed, only 64 bits of a 2K bit memory block are used and the remaining 1984 bits in that block are wasted.
In accordance with this invention a device is provided having programmable circuitry which includes a plurality of logic components, each having at least one programmable circuit, and a memory coupled to the plurality of logic components and being configurable to include at least two write ports and one read port, the memory being capable of performing multiple write and read operations substantially simultaneously.
In an alternative embodiment the memory of the device is configurable to include at least two read ports and one write port.
In still another alternative embodiment the memory of the device is configurable to include two write ports and two read ports.
In each embodiment each memory cell is accessible via any read port and any write port. This allows the memory to be operated in any of several different modes, including (1) operation as one large memory, or (2) operation as two, effectively separate, memories having any of a wide range of relative sizes.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.